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Hybrid Flip-Chip Integration of a 40 Gb/s DPSK Receiver Comprising a Balanced Photodetector on a DLI-SOI Board
Hybrid Flip-Chip Integration DPSK Receiver Comprising Balanced Photodetector DLI-SOI Board
2015/8/4
A DPSK receiver concept using flipchip hybrid integration of InP photodetectors on SOI boards with optical decoder is presented. Horizontal waveguiding enables low-cost production for high data rates.
Design of a 10Gbps Optical Burst Mode DPSK Receiver for Data and Clock Recovery
Optical Burst Mode DPSK Receiver Clock Recovery
2015/8/3
We present a 10Gbps DPSK burst mode receiver with zero latency clock synchronization. Concatenated phase-shift and resonator techniques maintain an NRZ data clock component over >1024 bit guard interv...